(1) Field of the Invention
The present invention relates to a word-line discharging circuit in a static-type semiconductor memory device of, for example, an emitter-coupled logic device, an integrated injection logic device, and so forth, using bipolar transistors.
(2) Description of the Prior Art
Generally, in the above-mentioned static-type semiconductor memory device, memory cells in one row are connected between a word line and a hold line. In order to hold the memory status, i.e., the status of the flip-flop, of each memory cell, a holding current flows from the word line through the memory cell and the hold line to a holding current source. The selection of the word line is effected by boosting the electric potential of the word line using a word driver. In this case, since the word driver is an emitter follower, the time for changing the word line from an unselected state to a selected state, that is, the rise time of the word line, is short. However, the time for changing the word line from a selected state to an unselected state, that is, the fall time of the word line, depends on the amount of charge stored in the parasitic capacitances of the word line and on the amount of holding current. This is because the emitter follower, i.e., the word driver, is cut off during the fall time. However, recently, semiconductor memory devices of large scale and low power consumption have been developed. Accordingly, the amount of holding current is becoming smaller so that the fall time of the word line tends to become long.
In order to shorten the fall time of the above-mentioned word line, a word-line discharging circuit has been employed for conducting a concentrated discharge current through the word line which is transferred from a selected state to an unselected state. That is, for conducting a discharge current, in addition to the regular holding current, through the above-mentioned word line, and for keeping the discharging current flowing through the above-mentioned word line for a certain time period.
A conventional word-line discharging circuit comprises, for each word line, a first transistor which is an emitter follower and which is switched in response to the electric potential of the word line, a time-constant circuit consisting of a first resistor and a capacitor, a second transistor switched by the output of the time-constant circuit, and a second resistor connected between the base of the second transistor and a common bias-current source. The second transistor has a collector connected to the corresponding hold line and an emitter directly connected to a common discharging current source. Therefore, the second transistors provided between the common discharging current source and the respective word lines constitute a current switch. That is, when a certain word line transfers from an unselected state to a selected state, the first transistor turns on and then after a time constant determined by the resistor and the capacitor of the time-constant circuit, the second transistor turns on so that the current flowing through the selected word line and the memory cells connected to the word line is increased by the current from the common discharging current source in addition to the regular holding current. Simultaneous with the transfer of the above-mentioned word line to the selected state, another word line transfers from a selected state to an unselected state so that the first transistor of the corresponding word line is turned off, and until the charges stored in the capacitor of the time-constant circuit are discharged through the second resistor, the discharging current from the common discharging current source is held. Therefore, the charges on the word line which has been changed to the unselected state are rapidly decreased so that the fall time of the word line is shortened.
In the above-described conventional circuit, a problem exists in that, along with the recent miniaturization and the development of a large-scale memory-cell structure, the amount of holding current flowing through the memory cells tends to become small. Also, along with the decrease in the current flowing from the word line through the memory cells to the word-line discharging circuit, the phenomenon of decreasing junction capacitance in the memory cell occurs. Therefore, when a word line transfers from a selected state to an unselected state, the value of the current flowing through the memory cell after the word-line potential falls is smaller than before the word-line potential falls. Thus, the amount of charge which can be stored in the memory cell is decreased after the word-line potential falls. As a result, after the word-line potential falls, the charges stored in the memory cell before the word-line potential falls, overflow to the word line so that the word-line potential is raised again. Thus, conventionally, there has been the problem of the phenomenon of double selection, in which the selected word line is again selected when the word line changes from a selected state to an unselected state.